Index of /hep/d0/ftp/run2b/l1cal/hardware/adf_2/drawings
Name Last modified Size Description
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adf_2_adc_10_bit.pdf 01-Nov-2004 17:08 27K
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adf_2_adc_10_bit.ps 01-Nov-2004 16:45 51K
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adf_2_capture_tt_neg_10_1_20050310.gif 11-Mar-2005 11:13 11K
adf_2_card_block_diagram.pdf 24-Jun-2004 17:24 61K
adf_2_card_block_diagram.ps 24-Jun-2004 17:22 115K
adf_2_circuit_board_1.pdf 03-Nov-2004 16:40 1.2M
adf_2_circuit_board_1.ps 03-Nov-2004 16:38 1.8M
adf_2_dc_dc_converter.pdf 08-Apr-2004 10:46 43K
adf_2_dc_dc_converter.ps 08-Apr-2004 10:45 92K
adf_2_differential_amp.pdf 14-Dec-2004 11:12 25K
adf_2_differential_amp.ps 14-Dec-2004 11:10 48K
adf_2_front_panel_silk_screen.pdf 25-Mar-2005 09:34 7.0K
adf_2_front_panel_silk_screen.ps 25-Mar-2005 09:33 60K
adf_2_front_panel_silk_screen_with_panel_outline.pdf 25-Mar-2005 09:41 8.1K
adf_2_front_panel_silk_screen_with_panel_outline.ps 25-Mar-2005 09:40 62K
adf_2_many_front_panels.pdf 24-Mar-2005 11:47 53K
adf_2_pal_signal_heirarchy.pdf 26-Aug-2004 16:17 68K
adf_2_pal_signal_heirarchy.ps 26-Aug-2004 15:59 148K
adf_2_pal_state_machine_timing_diagrams.pdf 27-Sep-2004 18:01 10K
adf_2_pal_state_machine_timing_diagrams.ps 27-Sep-2004 18:00 21K
adf_2_pal_top_level_schematic.ps 07-Feb-2005 15:19 148K
adf_2_pal_vme_invalid_cycle_timing_diagrams.pdf 26-Aug-2004 16:18 21K
adf_2_pal_vme_invalid_cycle_timing_diagrams.ps 26-Aug-2004 16:16 40K
adf_2_pal_vme_read_timing_diagrams.pdf 26-Aug-2004 16:18 24K
adf_2_pal_vme_read_timing_diagrams.ps 26-Aug-2004 16:17 44K
adf_2_pal_vme_write_timing_diagrams.pdf 26-Aug-2004 16:18 23K
adf_2_pal_vme_write_timing_diagrams.ps 26-Aug-2004 16:14 44K
adf_2_ped_dacs.pdf 01-Nov-2004 17:05 33K
adf_2_ped_dacs.ps 01-Nov-2004 16:49 61K
adf_2_power_up_supervisor.pdf 11-Apr-2005 11:48 43K
adf_2_power_up_supervisor.ps 11-Apr-2005 11:44 83K
adf_2_vme_timing_diagrams.ps 13-Jul-2004 12:41 58K
adf_crate_bx_clk_distribution.pdf 22-Mar-2004 14:23 11K
adf_crate_bx_clk_distribution.ps 22-Mar-2004 14:22 25K
board_control_pal_board_level_control.pdf 11-Jun-2004 14:22 34K
board_control_pal_board_level_control.ps 11-Jun-2004 14:21 65K
board_control_pal_fpga_configuration.pdf 01-Nov-2004 17:06 55K
board_control_pal_fpga_configuration.ps 01-Nov-2004 16:53 105K
board_control_pal_vme_interface.pdf 14-Dec-2004 11:13 24K
board_control_pal_vme_interface.ps 14-Dec-2004 11:10 47K
clock_bx_x8_generation.pdf 14-Dec-2004 11:14 48K
clock_bx_x8_generation.ps 14-Dec-2004 11:11 92K
clock_generation_timing.pdf 16-Jul-2004 13:41 17K
clock_generation_timing.ps 16-Jul-2004 12:59 35K
clock_signal_timing.pdf 16-Jul-2004 13:42 7.5K
clock_signal_timing.ps 16-Jul-2004 13:00 16K
data_path_fpga_output_to_channel_link.pdf 16-Aug-2005 13:57 39K
data_path_fpga_output_to_channel_link.ps 16-Aug-2005 13:54 74K
data_path_fpga_signal_processing.pdf 08-Dec-2005 11:53 53K
data_path_fpga_signal_processing.ps 08-Dec-2005 11:48 101K
et_lookup_memory_data.pdf 08-Dec-2005 11:52 14K
et_lookup_memory_data.ps 08-Dec-2005 11:50 29K
power_entry_and_dc_dc_converters.pdf 01-Nov-2004 17:09 26K
power_entry_and_dc_dc_converters.ps 01-Nov-2004 16:59 51K
run2b_l1_cal_trig_data_paths.pdf 21-Apr-2006 13:44 10K
scld_control_signal_distribution.pdf 14-Dec-2004 11:14 52K
scld_control_signal_distribution.ps 14-Dec-2004 11:11 98K
scld_logic_block_diagram.pdf 01-Jul-2004 21:13 40K
scld_logic_block_diagram.ps 01-Jul-2004 21:13 77K
scld_signal_timing.pdf 01-Jul-2004 21:27 20K
scld_signal_timing.ps 01-Jul-2004 21:26 39K
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